Dr.-Ing. Chi-Chia Sun

Dissertation

VLSI design concepts for iterative algorithms, 2011, [Online]

14 results

2012

C.-C. Sun, P. Donner, J. Götze, VLSI Implementation of a Configurable IP Core for Quantized Discrete Cosine and Integer Transforms, In International Journal of Circuit Theory and Applications, vol. 40, no. 11, pp. 1107-1126, 2012. [bibtex] [doi]

2011

H.-Y. Jheng, C.-C. Sun, S.-J. Ruan, J. Götze, FPGA Acceleration of Sparse Matrix-Vector Multiplication Based on Network-on-Chip, In 9th European Signal Processing Conference (EUSIPCO-2011), Barcelona, Spain, 2011. [bibtex]
C.-C. Sun, VLSI design concepts for iterative algorithms, Technische Universität Dortmund, 2011. [bibtex] [doi]

2010

C.-C. Sun, C. Zhang, J. Götze, A Configurable IP Core for Inverse Quantized Discrete Cosine and Integer Transform with Arbitrary Accuracy, In IEEE International Conference on Asia Pacific Circuits and Systems, Kuala Lumpur, Malaysia, 2010. [bibtex] [pdf]
C.-C. Sun, J. Götze, Parallel EVD and SVD Methods on Nanoscale Integrated Circuits, In 6th International Workshop on Parallel Matrix Algorithms and Applications, Basel, Switzerland, 2010. [bibtex]
C.-C. Sun, J. Götze, H.-Y. Jheng, S.-J. Ruan, Sparse Matrix-Vector Multiplication Based on Network-on-Chip in FPGA, In Advanced Topics on Embedded Systems and Applications in 7th IEEE International Conferences on Embedded Software and Systems, Bradford, UK, 2010. [bibtex]
C.-C. Sun, J. Götze, H.-Y. Jheng, S.-J. Ruan, Matrix-Vector Multiplication Based on Network-On-Chip, In Advances in Radio Science, 2010. [bibtex]

2009

C.-C. Sun, J. Götze, VLSI Circuit Design Concepts for Parallel Iterative Algorithms in Nanoscale, In The 2009 International Symposium on Communications and Information Technologies, Incheon, Korea, 2009. [bibtex] [pdf]
C.-C. Sun, P. Donner, J. Götze, Low-Complexity Multi-Purpose IP Core for Quantized Discrete Cosine and Integer Transform, In IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, 2009. [bibtex] [pdf]
C.-C. Sun, J. Götze, A VLSI Design Concept for Parallel Iterative Algorithms, In Advances in Radio Science, pp. 95-100, 2009. [bibtex]

2007

Method and circuit for performing a cordic based Loeffler discrete cosine transformation (DCT), particularly for signal processing, S.-J. Ruan, B. Heyne, J. Götze, C.-C. Sun, Pub. Info: EP1850597, 31.10.2007, 2007. [bibtex]
C.-C. Sun, S.-J. Ruan, B. Heyne, J. Götze, Low-power and high-quality Cordic-based Loeffler DCT for signal processing, In IET Circuits, Devices & Systems, vol. 6, no. 1, pp. 453-461, 2007. [bibtex]

2006

B. Heyne, C.-C. Sun, S.-J. Ruan, J. Götze, A Computationally Efficient High-Quality CORDIC based DCT, In Proc. 14th European Signal Processing Conference (Eusipco2006), Florence, Italy, 2006. [bibtex] [pdf]
C.-C. Sun, B. Heyne, S.-J. Ruan, J. Götze, A Low-Power and High-Quality CORDIC based Loeffler DCT for signal processing, In Proc. Int. Symposium on VLSI Design, Automation & Test (VLSI-DAT), Hsinchu, Taiwan, pp. 102 - 105, 2006. [bibtex]