Zum Inhalt
Fakultät für Elektrotechnik und Informationstechnik

Dissertation

Sparse matrix-vector multiplication based on network-on-chip
Hut, München, 2015, [Link]

 

Werdegang

 

Zeitraum Beschreibung
Juni 2005 B.Sc. Electrical Engineering, Al-Baath University, Syria
September 2006 – September 2008 Instrumentation and Control Engineer, Petrofac Oil & Gas EPC, UAE
Oktober 2008 – Oktober 2010 M.Sc. Automation and Robotics, TU Dortmund
Februar 2011 – Dezember 2016 Wissenschaftlicher Angestellter am AG Datentechnik, TU Dortmund

Veröffentlichungen

8 Einträge

2015

  • A. Mansour, Sparse matrix-vector multiplication based on network-on-chip, Hut, München, 2015. [bibtex]

2014

  • A. Mansour, J. Götze, W.-C. Hsu, S.-J. Ruan, Sparse Matrix-Vector Multiplication: A Data Mapping-Based Architecture, In IEEE 15th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2014), Hong Kong, 2014. [bibtex]

2013

  • A. Mansour, J. Götze, Inexact Sparse Matrix Multiplication on Parallel Hardware, In URSI Kleinheubacher Tagung 2013, Miltenberg, Germany, 2013. [bibtex]
  • A. Mansour, J. Götze, Inexact Sparse Matrix Vector Multiplication in Krylov Subspace Methods: An Application-Oriented Reduction Method, In Parallel Processing and Applied Mathematics, Springer Berlin Heidelberg, vol. 8384, pp. 534-544, 2013. [bibtex]
  • A. Mansour, J. Götze, Utilizing Robustness of Krylov Subspace Methods in Reducing the Effort of Sparse Matrix Vector Multiplication, In Procedia Computer Science, vol. 18, pp. 2406-2409, 2013. [bibtex] [doi]

2012

  • A. Mansour, J. Götze, An OMNeT++ Based Network-on-Chip Simulator for Embedded Systems, In IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2012), Kaohsiung, Taiwan, 2012. [bibtex]
  • A. Mansour, J. Götze, Sparse Matrix-Vector Multiplication Based on Network-on-Chip: On Data Mapping, In International Symposium on Parallel Architectures, Algorithms and Programming (PAAP 2012), Taipei, Taiwan, 2012. [bibtex]
  • A. Mansour, J. Götze, Sparse Matrix-Vector Multipication Using Network-on-Chip, In 7th International Workshop on Parallel Matrix Algorithms and Applications (PMAA 2012), London, UK, 2012. [bibtex]